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CMOS STATIC RAM 64K (64K x 1-BIT) Integrated Device Technology, Inc. IDT7187S IDT7187L FEATURES: * High speed (equal access and cycle time) -- Military: 25/35/45/55/70/85ns (max.) * Low power consumption * Battery backup operation--2V data retention (L version only) * JEDEC standard high-density 22-pin ceramic DIP, 22-pin leadless chip carrier * Produced with advanced CMOS high-performance technology * Separate data input and output * Input and output directly TTL-compatible * Military product compliant to MIL-STD-883, Class B DESCRIPTION: The IDT7187 is a 65,536-bit high-speed static RAM organized as 64K x 1. It is fabricated using IDT's highperformance, high-reliability CMOS technology. Access times as fast as 25ns are available. Both the standard (S) and low-power (L) versions of the IDT7187 provide two standby modes--ISB and ISB1. ISB provides low-power operation; ISB1 provides ultra-low-power operation. The low-power (L) version also provides the capability for data retention using battery backup. When using a 2V battery, the circuit typically consumes only 30W. Ease of system design is achieved by the IDT7187 with full asynchronous operation, along with matching access and cycle times. The device is packaged in an industry standard 22-pin, 300 mil ceramic DIP, or 22-pin leadless chip carriers. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM A A VCC A A A A A ROW SELECT 65,536-BIT MEMORY ARRAY GND CS DATAIN COLUMN I/O DATAOUT WE A A A A A A A 2986 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY TEMPERATURE RANGE (c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. AUGUST 1996 6.2 2986/7 1 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE PIN CONFIGURATIONS INDEX GND DATAIN A0 A1 A2 A3 A4 A5 A6 A7 DATAOUT WE GND 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 D22-1 17 16 15 14 13 12 VCC A15 A14 A13 A12 A11 A10 A9 A8 DATAIN CS 2986 drw 02 A1 A0 VCC A 15 2 3 4 5 6 7 8 9 10 11 12 13 1 22 21 20 19 18 A2 A3 A4 A5 A6 A7 DATAOUT L22-1 17 16 15 14 A14 A13 A12 A11 A10 A9 A8 WE CS 2986 drw 03 DIP TOP VIEW 22-PIN LCC TOP VIEW PIN DESCRIPTIONS Name A0-A15 Description Address Inputs Chip Select Write Enable Power Data Input Data Output Ground 2986 tbl 01 TRUTH TABLE(1) Mode Standby Read Write CS H L L WE X H L Output High-Z DOUT High-Z Power Standby Active Active 2986 tbl 02 CS WE VCC DATAIN DATAOUT GND NOTE: 1. H = VIH, L = VIL, X = don't care. 6.2 2 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM Rating Com'l. Mil. Unit V Terminal Voltage -0.5 to +7.0 -0.5 to +7.0 with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current 0 to +70 -55 to +125 CAPACITANCE (TA = +25C, F = 1.0MHZ) Symbol CIN COUT C C C W mA Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 8 Unit pF pF TA TBIAS TSTG PT IOUT NOTE: 2986 tbl 04 1. This parameter is determined by device characterization, but is not production tested. -55 to +125 -65 to +135 -55 to +125 -65 to +150 1.0 50 1.0 50 RECOMMENDED DC OPERATING CONDITIONS Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 -- -- Max. 5.5 0 6.0 0.8 Unit V V V V NOTE: 2986 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NOTE: 2986 tbl 05 1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Military Commercial Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5V 10% 5V 10% 2986 tbl 06 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%) IDT7187S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VCC = Max., VIN = GND to VCC MIL. COM'L. MIL. COM'L. Min. -- -- -- -- -- 2.4 Max. 10 5 10 5 0.5 0.4 -- IDT7187L Min. -- -- -- -- -- -- 2.4 Max. 5 2 5 2 0.5 0.4 -- Unit A A V V 2986 tbl 07 VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 10mA, VCC = Min. IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. 6.2 3 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5V 10%, VLC = 0.2V, VHC = VCC - 0.2V) 7187S25 7187L25 Symbol ICC1 Parameter Operating Power Supply Current CS = VIL, Outputs Open VCC = Max., f = 0(2) Dynamic Operating Current CS = VIL, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS VHC, VCC=Max., VIN VHC or VIN VLC, f = 0(2) Power S L S L S L S L Com'l. Mil. 7187S35 7187L35 Com'l. Mil. 7187S45 7187L45 Com'l. Mil. 7187S55/70 7187L55/70 Com'l. Mil. 7187S85 7187L85 Com'l. Mil. Unit mA -- -- -- -- -- -- -- -- 105 85 130 110 55 50 20 1.5 -- -- -- -- -- -- -- -- 105 85 120 100 50 40 20 1.5 -- -- -- -- -- -- -- -- 105 85 120 95 50 35 20 1.5 -- -- -- -- -- -- -- -- 105 85 120 90 50 30/28 20 1.5 -- -- -- -- -- -- -- -- 105 85 120 90 50 28 20 1.5 ICC2 mA ISB mA ISB1 mA NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change. 2986 tbl 08 DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only) VHC = VCC - 0.2V, VLC = 0.2V Typ. (1) VCC @ Symbol VDR ICCDR tCDR(3) tR(3) |ILI| (3) Max. VCC @ 2.0V -- 600 150 -- -- 2 3.0V -- 900 225 -- -- 2 Unit V A ns ns A 2986 tbl 09 Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Input Leakage Current Test Condition -- MIL. COM'L. Min. 2.0 -- -- 0 tRC(2) -- 2.0v -- 10 10 -- -- -- 3.0V -- 15 15 -- -- -- CS VHC VIN VHC or VLC NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed, but not tested. LOW VCC DATA RETENTION WAVEFORM DATA RETENTION MODE 4.5V V DR 2V tR V IH VDR 2986 drw 04 V CC 4.5V tCDR CS V IH 6.2 4 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2 2986 tbl 10 5V 480 DATAOUT 255 30pF* 5V 480 DATAOUT 255 5pF* 2986 drw 05 2986 drw 06 Figure 1. AC Test Load *Includes scope and jig capacitances Figure 2. AC Test Load (for tHZ, tLZ, tWZ and tOW) AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges) 7187S25 7187L25 7187S35/45(1) 7187L35/45(1) 7187S55(1) 7187L55(1) 7187S70(1) 7187L70(1) 7187S85(1) 7187L85(1) Symbol Read Cycle tRC tAA tACS tOH tLZ (2) (2) (2) (2) Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change Output Selection to Output in Low-Z Chip Deselect to Output in High-Z Chip Select to Power-Up Time Chip Deselect to Power-Down Time 25 -- -- 5 5 -- 0 -- -- 25 25 -- -- 12 -- 20 35/45 -- -- 5 5 -- 0 -- -- 35/45 35/45 -- -- 17/20 -- 30/35 55 -- -- 5 5 -- 0 -- -- 55 55 -- -- 30 -- 35 70 -- -- 5 5 -- 0 -- -- 70 70 -- -- 30 -- 35 85 -- -- 5 5 -- 0 -- -- 85 85 -- -- 40 -- 40 ns ns ns ns ns ns ns ns 2986 tbl 11 tHZ tPU tPD NOTES: 1. -55C to +125C temperature range only. 2. This parameter guaranteed but not tested. 6.2 5 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1 (1,2) tRC (5) ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID 2986 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 2 CS (1,3) t RC (5) tACS tLZ DATAOUT tPU VCC SUPPLY CURRENT ICC ISB (4) t HZ (4) DATA VALID tPD HIGH IMPEDANCE 2986 drw 08 NOTES: 1. WE is HIGH for Read cycle. 2. CS is LOW for Read cycle. 3. Address valid prior to or coincident with CS transition LOW. 4. Transition is measured 200mV from steady state voltage with specified loading in Figure 2. 5. All Read cycle timings are referenced from the last valid address to the first transitioning address. AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges) 7187S25 7187L25 7187S35/45(1) 7187S55(1) 7187L35/45(1) 7187L55(1) 7187S70(1) 7187L70(1) 7187S85(1) 7187L85(1) Symbol Write Cycle tWC tCW tAW tAS tWP tWR tDW tDH tWZ (2) (2) Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Write Enable to Output in High-Z Output Active from End-of-Write 25 20 20 0 20 0 15 5 -- 0 -- -- -- -- -- -- -- -- 12 -- 35/45 25/40 25/40 0 20/25 0 15/25 5 -- 0 -- -- -- -- -- -- -- -- 15/30 -- 55 50 50 0 35 0 25 5 -- 0 -- -- -- -- -- -- -- -- 30 -- 70 55 55 0 40 0 30 5 -- 0 -- -- -- -- -- -- -- -- 30 -- 85 65 65 0 45 0 35 5 -- 0 -- -- -- -- -- -- -- -- 40 -- ns ns ns ns ns ns ns ns ns ns 2986 tbl 12 tOW NOTES: 1. -55C to +125C temperature range only. 2. This parameter guaranteed but not tested. 6.2 6 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING) WE tWC ADDRESS tAW CS tAS WE t WZ DATA OUT t DW DATA IN t DH (5) (1,2,3,4) tWP tWR tOW (5) VALID DATA 2986 drw 09 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured 200mV from steady state with a 5pF load (including scope and jig). TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING) CS t WC ADDRESS tAW CS tAS WE t DW DATA IN t DH VALID DATA tCW t tWR (3) (1,2,4) 2986 drw 10 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured 200mV from steady state with a 5pF load (including scope and jig). 6.2 7 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE ORDERING INFORMATION IDT7187 Device Type X Power XX Speed X Package X Process/ Temperature Range B Military (-55C to +125C) Compliant to MIL-STD-883, Class B D L22 300 mil Ceramic DIP (D22-1) Leadless Chip Carrier (L22-1) 25 35 45 55 70 85 Speed in nanoseconds S L Standard Power Low Power 2989 drw 11 6.2 8 |
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